Ben Cohen – SystemVerilog Books and papers

BOOKS

• Knowledge-Driven AI for SystemVerilog Assertions: A Verification Framework of Methodologies, Processes, and Coding Rules 2026
  Book ships with downloadable RAG-SVA Files
  Paper copy (Amazon) | PDF version (Payhip) | TOC, Sample
  |For Indian Edition ($38) Contact ben_cohen@systemverilog.us
• Fast-Tracking SVA through Exposure: Core Usage, Concepts, AI Integration 2025
  Paper copy (Amazon) | PDF version (Payhip) | TOC, Sample (Amazon) | Perplexity Review
• SystemVerilog Assertions Handbook Revised 4th edition 2023
  PDF version ($55) | Paper Edition (USA) | Indian Edition
• 𝗦𝘆𝘀𝘁𝗲𝗺𝗩𝗲𝗿𝗶𝗹𝗼𝗴 𝗔𝘀𝘀𝗲𝗿𝘁𝗶𝗼𝗻𝘀 𝗛𝗮𝗻𝗱𝗯𝗼𝗼𝗸, 𝟰𝘁𝗵 𝗘𝗱𝗶𝘁𝗶𝗼𝗻 𝗶𝗻 𝗖𝗵𝗶𝗻𝗲𝘀𝗲
  𝗖𝗵𝗶𝗻𝗲𝘀𝗲 𝗽𝘂𝗯𝗹𝗶𝘀𝗵𝗲𝗿: 𝗖𝗵𝗶𝗻𝗮 𝗦𝗰𝗶𝗲𝗻𝗰𝗲 𝗣𝘂𝗯𝗹𝗶𝘀𝗵𝗶𝗻𝗴 𝗠𝗲𝗱𝗶𝗮 & 𝗟𝘁𝗱. (Science Press)
  𝗧𝗿𝗮𝗻𝘀𝗹𝗮𝘁𝗼𝗿𝘀: Sun Jian 孙健、Wei Haoran 魏浩然
  𝗔𝗯𝗼𝘂𝘁: SystemVerilogAssertionsHandbook_Chinese_revised.pdf
• A Pragmatic Approach to VMM Adoption … a SV Framework for Testbenches (2007)
  PDF | Code
• Real Chip Design and Verification Using Verilog and VHDL ($3)
  PDF (Payhip) | )
• Component Design by Example … A step-step process using VHDL with UART as vehicle
  Link | PDF | Code | Code (tar)
• Using PSL/Sugar with Verilog and VHDL
  (Two editions, translated to Japanese by Cadence)
• VHDL Coding Styles and Methodologies ... an in-depth tutorial
  (Two editions: 1995, 1999)
• VHDL Answers to Frequently Asked Questions
  (Two editions, evolved from comp.lang.vhdl forum)

PAPERS

• OVL Arbiter, 𝗖𝗹𝗮𝘂𝗱𝗲 𝘄𝗶𝘁𝗵 𝘃𝘀. 𝘄𝗶𝘁𝗵𝗼𝘂𝘁 𝗦𝗩𝗔-𝗥𝗔𝗚 𝗳𝗼𝗿 𝗙𝗼𝗿𝗺𝗮𝗹 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻
• 𝗔𝗜-𝗔𝘀𝘀𝗶𝘀𝘁𝗲𝗱 FV 𝗼𝗳 𝗮 SV 𝗣𝗮𝗿𝗸𝗶𝗻𝗴 𝗟𝗼𝘁 𝗖𝗼𝗻𝘁𝗿𝗼𝗹𝗹𝗲𝗿
• grnt -> req, Claude LLM vs Claude LLM + RAG
• 𝗣𝗮𝗽𝗲𝗿: 𝗜𝘁'𝘀 𝘁𝗵𝗲 𝗥𝗲𝗾𝘂𝗶𝗿𝗲𝗺𝗲𝗻𝘁𝘀, 𝗦𝗧𝗨𝗣𝗜𝗗!
• Post: Path for engr for effective solutions
• 𝗣𝗔𝗣𝗘𝗥: 𝗖𝗼𝗻𝘃𝗲𝗿𝘁𝗶𝗻𝗴 𝗟𝗲𝗴𝗮𝗰𝘆 𝗣𝗦𝗟-𝗦𝗜𝗠 𝘁𝗼 𝗦𝗩𝗔-𝗙𝗩-𝗥𝗲𝗮𝗱𝘆 𝗖𝗼𝗱𝗲
• 𝗣𝗔𝗣𝗘𝗥: 𝗖𝗼𝗻𝘃𝗲𝗿𝘁𝗶𝗻𝗴 𝗟𝗲𝗴𝗮𝗰𝘆 VHDL 𝘁𝗼 𝗦𝗩𝗔-𝗙𝗩-𝗥𝗲𝗮𝗱𝘆 𝗖𝗼𝗱𝗲 + SPECS
• 𝗣𝗔𝗣𝗘𝗥: 𝗖𝗼𝗻𝘃𝗲𝗿𝘁𝗶𝗻𝗴 SV/SVA 𝘁𝗼 VHDL/PSL
• Understanding the SVA Engine Using the Fork-Join Model
• Reflections on Users’ Experiences with SVA, part 1
• Understanding Assertion Processing Within a Time Step
• Reflections on Users’ Experiences with SVA, part 2
• Understanding and Using Immediate Assertions
• SVA Package: Dynamic and range delays and repeats
• SUPPORT LOGIC AND THE always PROPERTY
• SVA in a UVM Class-based Environment (alt link)
• SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter (code)
• Getting started with verification with SystemVerilog
• Understanding SVA Degeneracy (alt link)
• Leveraging Bing GPT-4 for Digital Design and Verification with SystemVerilog and Assertions (related)
• Understanding the within Operator
• The Traditional Req/Ack Handshake, It’s More Complicated Than You Think!
• DYNAMIC DATA STRUCTURES IN ASSERTIONS
• (intersect) vs (throughout, until, until_with, within)