/* I am writing a property of below specification: "my_seq to my_seq delay should not be less than my_timing." NOTE: I have to use the variable t because the timing needs to be calculated from other variables in my actual design. I tried not when writing the property. property my_prop; int t; @(negedge clk) disable iff (!rstn) my_seq |-> not (##0 (1, t = my_timing - 1) ##1 (1, t = t - 1)[*0:$] ##1 my_seq ##0 (t > 0)); endproperty */ import uvm_pkg::*; `include "uvm_macros.svh" module top; bit clk, a, b, rstn=1'b1; int my_timing= 4; default clocking @(posedge clk); endclocking initial forever #10 clk=!clk; sequence my_seq; ( a ##1 b); endsequence // "my_seq to my_seq delay should not be less than my_timing." // "my_seq to my_seq delay should be >= than my_timing." property my_prop; int t, count=0; @(negedge clk) disable iff (!rstn) (my_seq, t = my_timing - 1) |-> ##1 first_match((1, count=count+1'b1)[*0:$] ##1 my_seq) ##0 (count >= t); endproperty ap_my_prop: assert property(my_prop); initial begin repeat(200) begin @(posedge clk); if (!randomize(a, b) with { a dist {1'b1:=1, 1'b0:=3}; b dist {1'b1:=1, 1'b0:=2}; }) `uvm_error("MYERR", "This is a randomize error") end $stop; end endmodule