/* I have two states s0 and s1, and three clocks clk1, clk2, clk3. In s0 state clk1 and clk2 are active, and in s1 state clk3 is active. I need to fire an assertion when in state s0 if no clk is detected (in this case clk1 and clk2) and when in state s1 if clk33 is not detected. */ module top; timeunit 1ns; timeprecision 100ps; // `include "uvm_macros.svh" import uvm_pkg::*; typedef enum {ST0, ST1} st_t; bit clk0=0,clk1, clk2, clk3; bit active1, active2, active3; st_t state; bit done, err; event e; let P1=7; let P2=8; let P3=10; // periods of the clocks initial forever #3 clk0 = !clk0; // for test always_comb if (err) clk1=1'b0; else if (state==ST0) clk1= clk0; else clk1=1'b0; initial forever begin : ALIVE1 t_clk1(); wait (done); //@ (done); done=0; end task automatic t_clk1(); fork PERIOD1: begin #P1; active1=1'b0; end CLOCK1: begin @(clk1); active1=1'b1; disable PERIOD1; end join_any done=1; ->e; endtask always begin @(posedge done); #10 if(state==ST0) am_st0_clk1: assert(active1); end always begin // FSM repeat(3) begin #100 state= ST0; #100 state=ST1; end end initial begin err=0; #22 err=1; ; // error injection #44 err=0; end endmodule