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(SOFT COVER) SystemVerilog Assertions Handbook, 3rd Edition with IEEE 1800-2012  SVA3rdE_preface_toc.pdf  sva3rdE_cover.jpg   The book is now available for immediate shipment .    ISBN    978-0-9705394-3-6          $135       The Amazon Payments logo is a trademark of Amazon.com, Inc. or its affiliates.	3
* (HARD COVER) SystemVerilog Assertions Handbook, 3rd Edition with IEEE 1800-2012  The book is now available for immediate shipment.    ISBN    978-0-9705394-3-6          $170
* A Pragmatic Approach to VMM Adoption        ISBN 0-9705394-9-5          $100
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, ISBN 0-9705394-6-0              $60    * Japanese Version: Using PSL/Sugar, 1st Edition    ISBN 0-9705394-5-2              $45
* Real Chip Design and Verification Using Verilog and VHDL,  ISBN 0-9705394-2-8               $135
* Component Design by Example    ISBN 0-9705394-0-1              $60

OTHER BOOKS
** VHDL Coding Styles and Methodologies, 2nd edition (March 31, 1999), Ben Cohen
http://www.springer.com/engineering/circuits+%26+systems/book/978-0-7923-8474-8

** VHDL Answers to Frequently Asked Questions, 2nd ed., 1998, Cohen, Ben With CD-ROM
http://www.springer.com/engineering/circuits+%26+systems/book/978-0-7923-8115-0
For Stuart Sutherland Training:
* SystemVerilog Assertions,
* SystemVerilog Verification
* SystemVerilog Design
Contact:  Sutherland-hdl